This invention relates to a logic simulator for use in carrying out logic simulation of a simulation model of a logic circuit.
Such logical simulation of the simulation model is effective in designing logic circuits. The logical simulation is generally carried out by the use of software and is therefore software simulation in the art. The software simulation must actually be carried out in sequence for individual functional operators of a description descriptive of the simulation model. The sequential simulation requires a long simulation time. Such a simulation time is enormously long when the simulation model is, for example, a large scale logic circuit.
As a logic simulator which can shorten the simulation time, a hardware tool is proposed for use in simulating the simulation model. The hardware tool is called a hardware simulator in the art. As the hardware simulator, a dynamic gate array is disclosed by Kanji Ohmori in U.S. Pat. No. 4,541,071 assigned to the instant assignee. The hardware simulator is for use in simulating an overall operation which is carried out by a gate assembly comprising a plurality of gates. With this hardware simulator, each logic operation of the gates is simulated in consideration of those logic states of each gate which are determined by permutations. Thus, the hardware simulator can deal with the description on a gate level. However, no disclosure is made in the Ohmori Patent about dealing with the description of a functional level.